The semiconductor industry has seen tremendous advances in technology in recent years which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
In the past the die and package were first attached and then were wire bonded. The wire bonding procedure is simple in concept. A thin (0.7 to 1.0 mil) wire is first bonded to the chip bonding pad and spanned to the inner lead of the package lead frame. The third action was to bond the wire to the inner lead. Lastly, the wire is clipped and the entire process repeated at the next bonding pad. While simple in concept and procedure, wire bonding was critical because of the precise wire placement and electrical contact requirements. In addition to accurate placement, each and every wire must make a good electrical contact at both ends, span between the pad and the inner lead in a prescribed loop without kinks and be at a safe distance from neighboring lead wires. Wire loops in these packages are 8 to 12 mils, while those of ultrathin packages are 4 to 5 mils. The distance between adjacent wires is called the pitch of the bonding. Wire bonding has been done with either gold or aluminum wires. Both types of wire are highly conductive and ductile enough to withstand deformation during the bonding steps and remain strong and reliable.
Wire bonding between a die and a package has several problems. One problem is that a wire bond attachment to a die limits the number of pads and placement of the pads on the die. In addition, minimum height limits are imposed by the required wire loops. Another problem is that there is a chance of electrical performance problems or shorting if the wires come too close to each other. The wire bonds also require two bonds and must be placed one-by-one and there are resistances associated with each bond. The wires are also relatively long.
To increase the number of pad sites available for a die and to address the problems stated above and other problems, dies were provided with deposited metal bumps on each bonding pad. The bonding pads were also moved to the side of the die nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Connection to the package is made when the chip is flipped over and soldered. As a result, the dies are commonly called flip chips in the industry. Each bump connects to a corresponding package inner lead. The packages which result are lower profile and have lower electrical resistance and a shortened electrical path. The plurality of ball-shaped conductive bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. The packages are occasionally referred to as "Ball Grid Array" (BGA) or "Area Grid Array" packages or Chip Size Packages (CSP's).
A typical BGA package is characterized by a large number of solder balls disposed in an array on a surface of the package. It is not uncommon to have hundreds of solder balls in an array. The BGA package is assembled to a matching array of conductive pads. The pads are connected to other devices within a substrate or circuitry on a circuit board. Heat is applied to reflow the solder balls (bumps) on the package, thereby wetting the pads on the substrates and, once cooled, forming electrical connections between the package and the semiconductor device contained in the package and the substrate.
The introduction of flip chips and Ball Grid Array (BGA) packages to the semiconductor industry have brought several new manufacturing and assembly challenges. One of the more significant problems is finding an efficient, cost-effective technique for applying the solder ball contacts to the die or package surface. The die surface is usually formed from an electrically insulating material, usually silicon dioxide, with a pattern of metallized pads disposed thereupon for connecting to the package. The package is attached to an external system via a circuit board.
One of the larger challenges is keeping the height of solder ball contacts substantially uniform. This is a critical factor for successful attachment of flip chips to BGA-type packages. If one or more balls are significantly shorter than others it becomes highly likely that these smaller (shorter) contacts will completely miss their mating contact pads and will fail to form an electrical connection between the semiconductor device and the package. Another challenge is to keep the volume of solder associated with each pad essentially the same. If one pad is provided with too much solder, it may contact a neighboring pad on the die. This is an unwanted contact or short to another pad on the die.
In semiconductor manufacturing, a wafer is processed to form many individual chips (also known as dies). The wafer is diced to form the individual chips. Currently, bumps are formed on the chips or dies when they are still in wafer form. One of the final steps in the semiconductor manufacturing process is to form the actual pads on the surface of the chips. If the chips are flip chips, solder is then deposited on each pad. As mentioned above the amount per pad must be consistent so that a consistent set of bumps are formed when the solder is reflowed. Currently, solder is deposited at a rate of 0.6-0.8 micrometers/minute so that solder is deposited consistently on each pad across the wafer. Solder can be deposited at much faster rates, however, at the higher rates, depositing a consistent amount of solder on each pad is not possible. Differing amounts of solder on each pad may produce a short or an open as discussed above.
The slow deposition rate of solder onto the pads of each chip on a wafer is an obstacle to higher manufacturing rates. Many current manufacturing processes have slow throughput, and their deposition of solder onto the wafer can be a bottleneck in the manufacturing process.
As more and more capability is being designed into electronic devices, such as memory chips and microprocessor chips, the number of input/output elements or pads are being vastly increased. Therefore, a controlled process is also needed.